This presentation will review the current state of mm-wave radio technology as a vehicle for addressing this bandwidth/power-consumption crisis. The main promise of mm-wave radio is that it offers a route to power-efficient bandwidth - that is, the ability to greatly increase the available data rates without increasing the power consumption. To deliver successful mm- wave radio technology for general use, a number of multifaceted challenges will need to be tackled; these range all the way from basic integrated circuit design up to network design and network management. A complete effort on all of these challenges is necessary for successful commercial deployment of high- bandwidth, low power mm-wave networks.

Daniel Foty has some two decades of engineering and management experience in the mainstream of the technology industry - specifically in integrated circuits and wireless communications. He is the President his own consulting and research firm, Gilgamesh Associates, LLC, which works in very demanding areas of design and development - such as signal processing, wired/wireless communications, and ultra-low-power design. A serial entrepreneur, he is currently beginning to co-organize a new start-up company (Sarissa Radio, Inc., where he presently serves as Chief Technical Officer (CTO)) for the development of new technologies for ubiquitous ultra-high-speed, low-power, low-cost wireless interconnectivity. Dr. Foty is also an Adjunct Professor of Electrical Engineering at the Georgia Institute of Technology ("Georgia Tech"), and has served as an external graduate thesis examiner/advisor with the Tallinn University of Technology (Estonia), the University of Pretoria (South Africa), and the Tshwane University of Technology (South Africa). He is the author of the best-selling book, MOSFET Modeling with SPICE: Principles and Practice, which was published in 1997 by Prentice-Hall and is now in its third printing; a Vietnamese language edition was published in early 2006. In addition, he has authored or co-authored some 100 journal articles and conference presentations, and is a frequent plenary/keynote speaker at major international conferences throughout the world. Dr. Foty holds the B.S. degrees in Physics and Chemistry from Bates College, the M.S. degree in Electrical Engineering from the University of Illinois, and the Ph.D. degree in Materials Science from the University of Vermont..

Rich Goldman, VP of Corporate Marketing & Strategic Alliances at Synopsys, demonstrates the close linkage between the development of the semiconductor and space industries from the '50s to the present in his presentation "Tech and Space: A Symbiotic Relationship". Rich explores how the past achievements of both industries have paved the way for astounding new advances that will change the way we inhabit our own world and travel beyond it.

Synopsys' 25th anniversary gives us reason to celebrate 25 years of deep collaboration with a global design community that is relentlessly focused on innovation. Talented designers are forever pushing the boundaries of what is "possible" and as electronic content in our everyday devices skyrockets, the pressure on designers to develop differentiated products more quickly and cost effectively has never been greater.
This presentation breaks through the "black magic" of analog and digital design to demonstrate the benefits that interoperable PDKs can bring to custom design teams and highlights the role of Educational iPDKs (EDKs) for advancing research in universities, to help ensure designers can continue to successfully push the boundaries of what's possible.

Dealing with uncertainty inherent in the very nature of service-oriented computing, is one of the main challenges in building dependable service architectures. This uncertainty needs to be treated as a threat in a way similar to and in addition to faults, errors and failures, traditionally dealt with by the research community. The lack of sufficient evidence about the characteristics of the communication me dium, components and their possible dependencies makes it extremely difficult to achieve and predict (composite) service dependability which can vary over a wide range in a very random manner. This uncertainty of services running over the Internet and clouds exhibits itself through the unpredictable response times of messages and data transfers, difficulty to diagnose the root cause of failures, unknown common mode failures, etc. Distributed nature of web service communications establishes a time-probabilistic relationship between different servicing outcomes and failures modes. This causes a problem of optimal timeout setting and necessity of a trade-off between dependability and performance.

Dr.Sc. Anatoliy Gorbenko is an Associate Professor in Computer Science with the Department of Computer Systems and Networks at the National Aerospace University where he also gained his MSc (2000), PhD (2005) and Dr.Sc. (2012). A. Gorbenko has a solid mathematical and engineering background and extensive experience in developing dependability evaluation and performance benchmarking techniques for distributed computer systems, networks and service-oriented architectures. Within the Ukrainian scientific and technical centre DESSERT (http://www.stc-dessert.com/staff.php?id_staff=4) he leads the service-oriented systems dependability research group. A. Gorbenko recei ved a few grants of university of Newcaste-upon-Tyne (UK) as an invited fellow researcher. He is team leader of the TEMPUS-MASTAC, TEMPUS-SAFEGUARD and FP7-KhAI-ERA projects in area of critical computing, IT-infrastructure and embedded systems dependability and safety.

In recent years software development discipline has made significant advances in the area of program code entry, navigation and analysis which resulted in powerful integrated development environments, e.g. the open-source Eclipse IDE. The existing hardware development environments are lacking this progress and remain awkward. The situation is even worse in the open-source tools domain. At the same time RTL still remains today the primary abstraction level for hardware design entry and the state-of-the-art design flows need to cope with designs of enormous size. The algorithms used in the front-ends and back-ends of the RTL design tools are often based on methods developed years ago (e.g. Espresso in 1986 and Booldozer in 1996 from IBM) when scalability issues were less of a concern than they are now. Satisfying the scalability property together with the predicted technology scaling is a non-trivial task. Therefore the internal design representation models of the EDA tools are usually kept in-house and are as proprietary as the tools themselves.

This talk will present for the first time an open-source platform zamiaCAD for hardware design and analysis which is based on an open and highly scalable model. The platform addresses the above mentioned issues and offers academia a basis for implementation and evaluation of research algorithms related to hardware design, test and debug. At the same time it allows the industry significant productivity enhancement and lowers the barrier for applying the leading edge research results in real world designs.

As an example application implemented on the research platform there will be demonstrated an automated design error localization approach that relies both on simulation and static analysis.

Dr. Maksim Jenihhin is a senior research fellow at the Department of Computer Engineering at Tallinn University of Technology, Estonia. He received his MSc and PhD degrees from the same university in 2004 and 2008 respectively. His primary research interests include hardware functional verification and debug as well as manufacturing testing topics and EDA methodologies. He has co-authored more than 50 journal and conference papers. Maksim Jenihhin received an IBM Faculty Award in 2011.

Numerous destabilizing factors, both external (ambient temperature, radiation, etc.) and internal (signal distortion, crosstalk, etc.) in modern digital ICs significantly impact their functionality. Functional failures in the result of destabilizing factors should be taken into consideration during logic simulation stage, keeping simulation speed high. This requires development of new circuit models and new simulation algorithms enabling acquiring accurate simulation results not affecting simulation speed significantly.
Basic principles of construction of logic simulation systems with consideration of destabilizing factors are presented in the talk. New digital circuit models are presented which enable logic simulation with consideration of destabilizing factors with circuit level simulation accuracy and speed close to conventional logic simulators. Algorithms for destabilizing factor consideration in logic simulation are also presented, based on the presented circuit models.

Vazgen Melikyan is Professor, Doctor of Technical Sciences, Honorable Scientist of Armenia, Director of Educational Department of Synopsys Armenia CJSC and Head of Interfaculty Chair of "Microelectronic Circuits and Systems" (MCS) of State Engineering University of Armenia (SEUA).
V. Melikyan has a degree in Computer Science from the Yerevan Polytechnic Institute, Cybernetics Department, received his Ph.D. from the Moscow Engineering-Physics Institute and received the title of Associate Professor in Computer Science Supreme Certification Board in Moscow in 1985. He was granted the degree of Doctor of Technical Sciences in SEUA, Yerevan, 2006 and Academic rank of Professor in Technical Sciences in SEUA, Yerevan, 2006. The author of more than 180 scientific and 110 methodical publications, with more than 140 reports presented in international conferences, V. Melikyan has received numerous Best Paper Awards from multiple international scientific conferences, as well as several prizes from scientific contests. He is an Honorary Professor of a number of universities, including National Research University of Moscow Institute of Electronic Technology "MIET".
Additional accolades include being a member of the SEUA Scientific Council, Program Committee and Head of Sessions in various international scientific conferences, and Boards in defenses of dissertations. He is also the President of Program Committee of International Microelectronics Olympiad of Armenia, a member of RA Presidential Award Committee in IT sector.

Although the main objective of test will remain essentially the same - to ensure high quality low cost manufacturing test - the conditions and consequently also the solutions will undergo a significant evolution over the next couple of years. The key factors, that will have a big impact on how test will continue to evolve, will include: the semiconductor technology, design characteristics, and the design process. This talk will discuss what types of defects will have to be considered to provide the required test quality for the next technology nodes, including 3D, and what matching DFT methods will need to be deployed. Test compression was introduced a decade ago and it very quickly became the predominant DFT methodology. This talk will debate what will be the main DFT methodology for the next decade. Will it be compression, BIST, or a hybrid technology? What other advanced DFT techniques will be required? The designs are getting bigger and increasing often they are done by geographically distributed teams with a generous usage of IP cores, developed internally or acquired commercially. What is the expected impact of that on hierarchical DFT and pattern retargeting? The talk will discuss many of these challenges facing test but it will also highlight new opportunities for the research community.

Dr. Grzegorz Mrugalski is a development engineering director for the Silicon Test Solutions products at Mentor Graphics Poland. He received the M.S. and Ph.D. degrees in electrical engineering from the Poznan University of Technology, Poland, in 1995 and 2002, respectively. He has published more than 40 research papers in the area of design-for-test focusing on compression and diagnosis. He is a co-inventor of 15 US and 9 international patents. He is a co-author of the paper introducing Embedded Deterministic Test (EDT) technology at International Test Conference in 2002 - this technology is used in the first commercial test compression product TestKompress?. He was the co-recipient of the 2010 Best Paper Award at the IEEE European Test Symposium. He serves as a Program Committee Member of the Design, Automation and Test in Europe Conference.

The history of hardware description language goes back to 1960's when IMB introduced APL (A programming language) for their in- house digital circuit modeling and simulation. The early 1970's witnessed a rise of HDLs like AHPL (originally derivation of APL), DDL, CDL, and other primarily register transfer level (RTL) languages.

The advent of VHDL in the 1980's formalize RTL languages and gave a new meaning to electronic design automation (EDA), that now included simulation, synthesis, physical modeling, and tools for pre and post manufacturing test.

With the present changes occurring in digital system design trends, and system integration mixed simulation requirements, HDLs are being redefined. Today's HDLs present environments for representing mixed mechanical, analog and digital systems. The EDA tools based on such languages are responsible for mixed simulation, verification, testing, and automatic synthesis and placement.
This talk presents a history of HDLs and shows how these languages have shaped the way electronic systems are being design today.

Ricardo Reis is Full Professor and the Head of the Microelectronics Graduate Program at Federal University of Rio Grande do Sul - UFRGS. He is presently Vice-President of IEEE Circuits and Systems Society. He received the Electrical Engineering from the (UFRGS), Porto Alegre, Brazil, in 1978. In 1983, he received the Ph. D. degree from the Polytechnic Institute of Grenoble (INPG), France. His primary research interests include Physical Design Automation and Methodologies, CAD tools, Circuits Tolerant to Radiation, VLSI Design Methodologies and Microelectronics Education. He has published more than 250 hundred papers in journals and conferences proceedings (like IEEE Design & Test, ACM TODAES, IEEE JSSC, ISCAS, SBCCI, PATMOS, VLSI-SoC, DAC, DATE, ICCD, CICC, ASP-DAC, LATW). He is also author or co-author of several books. He got also some papers awards and he received an award as research of the year from the Fapergs (Science Foundation of Rio Grande do Sul), 2002. Silver Core award from IFIP. Ricardo Reis is research level 1A of the CNPq (Brazilian National Science Foundation) and head of several research projects supported by Government Agencies and Industry. Past head of the Graduate Program in Computer Science at UFRGS, where is a thesis advisor. He served as a General Chair or Program Chair of several conferences like the IFIP/IEEE VLSI-SoC, IEEE ISVLSI, IEEE LASCAS, Symposium on Integrated Circuits and Systems Design (SBCCI) and Congress of the Brazilian Microelectronics Society (SBMIcro). He is Past President of the Brazilian Computer Society and Past Vice-President of the Brazilian Microelectronics Society. Ricardo is member of the Editorial Board of IEEE Design&Test and chair of the Steering Committee of the IFIP/IEEE VLSI-SoC series of conferences. He is also member of the CEDA Technical Activities Committee. Ricardo Reis is a senior member of IEEE.

The talks starts with a short presentation of the evolution of Electronics and Microelectronics. Than it will cover a several trends in the design of micro and nanoelectronics circuits, including architectural issues, variability and sources of variability, EDA tools, physical design issues, printability, design of transistor networks, Layout Strategies, Regularity, 3D circuits, flexible electronics, new devices, Stretchable Silicon, Fault Tolerance, Tolerance to Radiation Effects, Factory Integration.

Relentless scaling of silicon fabrication technology coupled with lower design tolerances are making ICs increasing susceptible to wear-out related permanent faults as well as transient faults (soft errors). The errors upset the devices normal functioning, however many times it does not reflect to the application. In this talk we'll discuss various masking phenomena and mitigation techniques at various level of abstraction starting from device to application.A well known technique for tackling both transient and permanent faults is redundant execution, specifically space redundancy, wherein a program is executed redundantly on different processors, pipelines or functional units and the results are compared to detect faults. This talk will describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS)algorithm significantly reduces the power overhead of redundant execution without sacrificing performance. Using cycle accurate simulation combined with an architectural power model we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 76% (i.e, it needs about 24% additional energy in comparison with non fault tolerant architecture) with an associated mean performance penalty of only 1.2%. We also present an extension to our architecture that enables the use of cores with faulty functional units for redundant execution without a reduction in transient fault coverage. This extension enables the usage of faulty cores, thereby increasing yield and reliability with only a modest power-performance penalty over fault-free execution.

Virendra Singh is serving as an Associate Professor at Indian Institute of Technology (IIT) Bombay. He obtained Ph.D in Computer Science and Engineering from Nara Institute of Science and Technology (NAIST), Nara, Japan in 2005. He receive B.E and M.E in Electronics and Communication Engineering from Malaviya National Institute of Technology (MNIT), Jaipur, India in 1994 and 1996 respectively. Prior to joining IIT, he was a faculty member at Supercomputer Education and Research Centre (SERC), Indian Institute of Science (IISc), Bangalore from 2007 to 2011. He also served Central Electronics Engineering Research Institute (CEERI), Pilani, India (a national research Institute) as a Scientist for 10 years prior to joining IISc. His research interests are high performance computer architecture, testing and verification of high performance processors, fault tolerant computing, VLSI testing, design for test, formal verification of hardware designs, embedded system design, design for reliability, and CAD of VLSI Systems. He is a member of the IEEE, the ACM, the VSI, and life member of the IETE. He is a PC member of many conferences in the area of CA, CAD and VLSI such as ICCD, DATE, ETS, ATS, VLSI Design, IOLTS, ISVLSI, VLSI-SOC, ASPDAC. He is a co-founder of RASDAT (IEEE International Workshop on Reliability Aware System Design and Test) workshop.

We present a novel view on the Structurally Synthesized BDDs (SSBDD) as a model with inherent double topology for compact modeling of single faults and efficient reasoning of multiple faults. The nodes in SSBDDs represent lower level signal path topology in the original circuit, and the paths in SSBDD represent higher level topology of conditions to be processed during fault reasoning. The double topological view on SSBDDs allows to give easy explanation of the limitations of existing methods of multiple fault testing, and shows the ways how to avoid fault masking. A generalization of the test pair approach in a form of the concept of test groups is introduced for testing multiple faults. Differently from the known approaches, we don't target the faults as test objectives. Instead of that, the goal is to verify by test groups the correctness of a selected part of a circuit, represented by a group of nodes in SSBDD. The main power of the method is to facilitate fault diagnosis in the presence of multiple faults. The knowledge about identified correct parts of the circuit allows to extend step by step the core of the circuit proved as correct.

Raimund Ubar is the Head of Estonian Centre of Excellence for Integrated Electronic Systems and Biomedical Engineering, and a professor of computer engineering at Tallinn Technical University. He received his PhD degree in 1971 from the Bauman Technical University in Moscow, and the DSc degree in 1986 from the Institute of Computers of the Latvian Academy of Sciences. His main research interests include computer science, electronics design, digital test, technical diagnostics and dependability of embedded systems. He has published more than 400 papers and six books, lectured as a visiting professor in more than 25 universities in about 10 countries, and served as a General Chairman for many conferences. He is member of Estonian Academy of Sciences, Golden Core member of IEEE Computer Society, and Honorary professor of National University of Radioelectronics Charkiv, He has been a Chairman of Estonian Science Foundation, and a member of the Estonian Science Council. He was also a member of the Academic Advisory Board of the Estonian President, and is awarded from the Estonian Government by White Cross Orden of III Class.

This talk will coin some concepts that came to being as an engineer once made an arduous journey from EDA developer of a behavioral synthesis tool to ASIC designer and then on to teaching and research in academia. The EDA developer in disguise of logic design engineer found comfort in writing Perl scripts writing out Verilog rather than the ruthless practice of writing plain HDL. He defended this unorthodox practice with his invented buzzwords of "manual behavioral synthesis", "semi-automation", "RTL generators". Then, the design engineer in disguise of a professor taught his students what he did best "designing chip blocks" under a fancy sounding buzzword he invented "Hardware Design Patterns". Besides anecdotes, the talk will include specific examples where these concepts were needed/used and how they helped to solve engineering problems/bottlenecks.

H. Fatih Ugurdag is an assistant professor in the EE Dept. at Ozyegin University, and a consultant to the logic design and video processing group at Vestel Electronics, which is one of the largest consumer electronics OEMs in Europe controlling about 20% of the LCD-TV and STB market. Dr. Ugurdag got his BS in EE and BS in Physics from Bosporus University in 1986. He then received his MS and PhD in EE from Case Western Reserve University in Ohio in 1989 and 1995, respectively. He worked in the industry in the US between 1989-2004 and his employers included General Electric, General Motors, Lucent, Juniper, ARC, and Nvidia. His research interests include Computer Arithmetic, DSP Hardware, Reconfigurable Computing, Embedded Systems, and Video Processing. He is on the Editorial Board of Elsevier DSP Journal. He will chair IFIP/IEEE VLSI-SoC Conference in October 2013.

Negative Bias Temperature Instability (NBTI) has the potential to become one of the main limiting factors of reliability in nanometer scale devices due to its deleterious effects on PMOS transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance, i.e., accelerated aging of CMOS circuits. On the other hand, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest portion of a System-on-Chip (SoC). So, SRAM's robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime. This paper describes recent achievements involving an approach based on an On-Chip Aging Sensor (OCAS) to detect SRAM aging during system lifetime. OCAS is able to detect any specific aging state of a cell in the SRAM array. The strategy is based on the connection of an OCAS per SRAM column, which periodically performs monitoring of off-line write operations into the SRAM cells to detect aging. To prevent OCAS from aging by one side and from dissipating static power by the other side, OCAS circuitry is powered-off during idle periods. A complete set of Monte Carlo/HSPICE simulations for several technology corners of a commercial 65nm CMOS technology and for different cell aging conditions demonstrates the high sensor sensitivity to detect early aging states even in the presence of large process parameters variation. Thus, guarantying high memory reliability. Furthermore, area overhead and power consumption due to sensor insertion for different memory topologies have been checked and resulted in almost negligible values.

Keywords: Nano-scale SRAM; SRAM Reliability; NBTI; Aging Effect; On-Chip Aging Sensor, Process Variation.

Fabian Luis Vargas obtained his Ph.D. Degree in Microelectronics from the Institut National Polytechnique de Grenoble (INPG), France, in 1995. At present, he is Full Professor at the Catholic University (PUCRS) in Porto Alegre, Brazil. Among several activities, Prof. Vargas has served as Technical Committee Member or Guest-Editor in many IEEE-sponsored conferences and journals. He holds 6 BR and international patents, co-authored two books and published over 200 refereed papers. Prof. Vargas is researcher of the BR National Science Foundation since 1996. He co-founded the IEEE-Computer Society Latin American Test Technology Technical Council (LA-TTTC) in 1997 and the IEEE Latin American Test Workshop (LATW) in 2000. Prof. Vargas received the Meritorious Service Award of the IEEE Computer Society for providing significant services as chair of the IEEE Latin American Regional TTTC Group and the LATW for several times. Prof. Vargas is a Golden Core Member of the IEEE Computer Society.

Yervant Zorian - Chief Architect, Synopsys, USA, and General Chair of East-West Design & Test Symposium.

Previously a Distinguished Member of Technical Staff at AT&T Bell Laboratories and the Chief Technology Advisor of LogicVision Inc, Dr. Zorian received an MS from University of Southern California and a PhD from McGill University.

He is an adjunct professor at the University of British Columbia. He served as the IEEE (Institute of Electrical and Electronic Engineers) Computer Society Vice President for Conferences, Tutorials, and Technical Activities. He was elected twice as the President of IEEE Test Technology Technical Council (TTTC). He founded and chairs several IEEE conferences and serves as editor of scientific journals, including Editor-in-Chief Emeritus of the Design & Test of Computers Journal. He founded and chairs the IEEE 1500 Standardization Working Group.

On the Armenian side, Dr. Zorian is the chair of AGBU Silicon Valley Chapter, the Program Chairman of ArmTech Congress, and a member of the Board of Trustees of the American University of Armenia (AUA). In 1999, he received an honorary doctorate from the National Academy of Sciences of Armenia.

Dr Zorian has authored over 300 scientific papers, four books, holds 18 US patents, and received numerous best-paper awards and Bell Labs‚ R&D Achievement Award. A Fellow of IEEE, he was selected by Electiral Engineering Times among the top 13 influencers on the semiconductor industry. Dr. Zorian was the 2005 recipient of the prestigious IEEE Industrial Pioneer Award, and 2006 Hans Karlsson Award.