Jordi Carrabina, Prof. T., PhD. Leads the CEPHIS kaboratory at Universitat Autònoma de Barcelona (Spain). Main interests are Physically and Functionally flexible platforms and solutions for the implementation of Cyber-physical Systems using Reconfigurable computing and Printed Microelectronics Technologies.
He is Teaching Telecom, EE, and CS and MA of Telecom Engineering at UAB and Embedded Systems Master at UPV-EHU. During last 5 years he has co-authored more 30 papers in journals and conferences. He also leaded many European, national and regional R&D projects and contracts in the ICT domain and is active in the creation of spin-off and Intellectual Property items.
Guilhem Velve Casquillas is in charge of ELVESYS management as well as the support of the sisters companies arising from ELVESYS. Inside of ELVESYS, he is also in charge of the R&D on the scientific projects with strong potential of creation of new companies. Notably, he's PhD thesis enabled the development of the world fastest pathogenic detection system (FASTGENE technology). In 2014, this FASTGENE project won the Worldwide 2030 Innovation Contest organized by the French government.
Guilhem is a member of "Réseau Entreprendre" (Undertake Network) and also gives voluntary entrepreneurship lessons inside research institutes in order to help young scientists create their enterprise.
"Some inputs about inception of hardware technological start up in 21 century"
Prof. Fernando Corinto
Politecnico di Torino (Italy)
Prof. Fernando Corinto received the Masters' Degree in Electronic Engineering and the Ph.D. degree in Electronics and Communications Engineering from the Politecnico di Torino, in 2001 and 2005 respectively. He also received the European Doctorate from the Politecnico di Torino, in 2005. F. Corinto was awarded a Marie Curie Fellowship in 2004.
He is currently Associate Professor of Circuit Theory with the Department of Electronics and Telecommunications, Politecnico di Torino. His research activities are mainly on nonlinear circuits and systems, locally coupled nonlinear/nanoscale networks and memristor nanotechnology.
Prof. Corinto is co-author of 6 book chapters and more than 130 international journal and conference papers. Since 2010, he is Senior Member of the IEEE. He is also Chair of the IEEE CAS Technical Committee on "Cellular Nanoscale Networks and Array Computing" and member of the IEEE CAS Technical Committee on "Nonlinear Circuits and Systems". Prof. Corinto serves as Vice-Chair of the IEEE North Italy CASâ€šÂ Chapter. Prof. Corinto has been Associated Editor of the IEEE Trans. on Circuits and Systems - I for 2014-2015. He is also in the Editorial Board and Review Editor of the International Journal of Circuit Theory andâ€šÂ Applications since January 2015. Prof. Corinto is Vice Chair of the COST Action "Memristors -- Devices, Models, Circuits, Systems and Applications (MemoCiS)". Prof. Corinto has been DRESDEN Senior Fellows atâ€šÂ the Technische Universitat Dresden in 2013 and 2017. Prof. Corinto has been August- Wilhelm Scheer visiting professor at Technische Universitat Munchen in 2016 and he is also member of the Institute for Advancedâ€šÂ Study -Technische Universitat Munchen.
Dr. Slobodan Mijalkovic
Silvaco Europe, Cambridge, (UK)
Dr. Slobodan Mijalkovic is a Senior R&D Engineer at Silvaco Europe in Cambridge (UK), specialized in modeling for computer-aided design on process, device and circuit level. Before joining Silvaco Europe, he was a Principal Researcher in HiTeC Laboratory at Delft University of Technology in the Netherlands, where he led a team for standardization of the Mextram bipolar transistor model with Compact Model Coalition (CMC). Formerly, he was Assistant and Associate Professor with the Department of Microelectronics at Faculty of Electronics Engineering, University of Nis in Serbia.
Dr. Mijalkovic has authored more than 80 publications and a monograph Multigrid Methods for Process Simulation in the Springer book series Computational Microelectronics. He has set and chaired four editions of Compact Modeling for RF Application (CMRF) workshops that strongly contributed to the acceptance of Verilog-A as a standard HDL for compact modeling. He is currently a member of IEEE EDS Compact Modeling Committee.
"Advanced TFT Modeling for Technology and Circuit Design"
The well-established amorphous and polycrystalline silicon TFTs are increasingly struggling to meet the modern display design requirements. Rapidly emerging oxide and organic semiconductor TFTs appear to be new leading technologies for the next generation post-silicon displays. Some potential applications of the oxide and organic TFTs are also going far beyond display circuits, promising to become essential technology for future printed, flexible and neuromorphic electronic systems.
New models are required on two different levels to support electronic design automation of present and future oxide and organic TFT technology and circuits. Optimization of a TFT architecture and fabrication technology at device level requires physical TCAD models for charge distribution and carrier transport in oxide and organic semiconductors. On the other hand, efficient and accurate compact models are required to support simulation of oxide and organic TFT circuits. A range of peculiar features of charge distribution and transport in oxide and organic TFTs require special modeling consideration. The advanced TCAD models for oxide and organic TFTs will be demonstrated in simulation case studies including a mixed-mode simulation as a methodology to fulfill common device-circuit design objectives. A full-range charge-based TFT compact modelling approach, suitable for both oxide and organic TFTs, will be demonstrated in practical applications to TCAD generated and measured oxide and organic TFT static and dynamic electrical characteristics.
This talk will present for the first time an open-source platform zamiaCAD for hardware design and analysis which is based on an open and highly scalable model. The platform addresses the above mentioned issues and offers academia a basis for implementation and evaluation of research algorithms related to hardware design, test and debug. At the same time it allows the industry significant productivity enhancement and lowers the barrier for applying the leading edge research results in real world designs.
As an example application implemented on the research platform there will be demonstrated an automated design error localization approach that relies both on simulation and static analysis.
Dr. Maksim Jenihhin is a senior research fellow at the Department of Computer Engineering at Tallinn University of Technology, Estonia. He received his MSc and PhD degrees from the same university in 2004 and 2008 respectively. His primary research interests include hardware functional verification and debug as well as manufacturing testing topics and EDA methodologies. He has co-authored more than 50 journal and conference papers. Maksim Jenihhin received an IBM Faculty Award in 2011.
Dr. Mirjana Videnovic-Misic
University of Novi Sad (Serbia)
Dr. Mirjana Videnovic-Misic received her PhD degree from the University of Novi Sad, Serbia, in 2009. From 2010 to 2016 Dr. Videnovic-Misic was Assistant Professor at the Department of Electronics, Faculty of Technical Sciences, Novi Sad, Serbia. She was Fulbright Visiting Scholar at UC Berkeley from 09/2014-06/2015. Since July 2015 she is Marie Currie Fellow under the guidance of Professor Borivoje Nikolic. Dr. Videnovic-Misic was working at Berkeley Wireless Research Center (09/2014-01/2017) and R&D ST Microelectronics enter in Crolles, France (01/2017-06/2017). She is currently working on the next generation blocker resilient receiver topologies for full-duplex application. Her research interest includes noise modelling of submicron components, design and optimization of analog and radio-frequency integrated circuits for the next generation mobile devices.
"Analogue design optimization techniques for 5G in 28nm FD-SOI"
Dr. Yervant Zorian
Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.
Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science.
He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.